The present invention generally relates to data transmission with speeds of the order of magnitude of several Gigabits/sec between two clock domains, of which each may be constituted by e.g. a CPU, a part of an ATM switch or other equipment which sends and receives data. ATM allows transmission of large data quantities over arbitrary media with the use of data packages with a prescribed length and small overhead.
More specifically, the invention relates to a data transmission system, in which data streams are to be transmitted at a large speed between a sending clock domain and a receiving clock domain, which operate with mutually different clock speeds.
In two data transmission systems, which are operating with approximately the same clock frequency generated by two separate oscillators, one in each system, and which are to be connected and transmit data to each other, a certain drift may occur between the frequencies. Because of this a buffer must be inserted between the two systems, which may emit data faster than it receives it, or vice versa, depending on which system's clock frequency is the larger one.
In the U.S. Pat. No. 5,305,253 a memory with separate read and write buses, two address ring counters, one for write and one for read operations, and an alarm which detects when the buffer is empty and full, is described. Since it is very difficult to make memories with a reply time shorter than 7 ns without resorting to the use of GA, this solution is not usable at frequencies of the order of magnitude of Gigabits/sec.
In the U.S. Pat. No. 4,819,201 an asynchronous FIFO circuit is described which includes consecutive data storage registers, which relay incoming data if the following register is empty. When the FIFO circuit is empty data will accordingly be let through from the beginning of the register stack to its end. This may cause risk for degradation of data and is furthermore a slow solution.
Among other publications relating to the same subject, the following may be mentioned.
U.S. Pat. No. 5,319,597 "FIFO memory and line buffer",
U.S. Pat. No. 5,084,837 "FIFO buffer with folded data transmission path permitting selective bypass of storage",
U.S. Pat. No. 4,803,654 "Circular first-in, first-out buffer system for generating input and output addresses for read/write memory independently".